This invention relates to semiconductor devices, and more particularly to a method of aligning and holding semiconductor chips when mounting onto a package substrate.
When a semiconductor chip containing an integrated circuit is mounted face down, i.e., with the active circuitry toward the substrate, this is referred to as flip-chip assembly. Usually bonding pads are formed on the chip, and a matching, mirror-image set of bonding pads is formed on the substrate to receive the chip pads. Metallic bumps may be formed on the pads to facilitate bonding. The assembly must be subjected to a soldering operation, e.g., reflow soldering, to secure the mating pads on the chips and substrate. Alignment of the semiconductor chips in flip chip assembly of this type has been done using a specially-constructed jig employing split-field optics to align the chip pads to the substrate pads; the chips are then reflow soldered on this equipment, or else transported to a reflow furnace for permanent attachment. In either method, flux is ordinarily used. If the reflow is performed on the alignment equipment then flux is required to clean the oxides on the solder, because it is difficult to build an enclosure around the alignment and reflow mechanisms to exclude oxygen. If the reflow is performed in a separate system, then tack flux is used to maintain the chips in place, aligned with the substrate pads, during the transport from the alignment mechanism to the reflow equipment.
Not only does the method just described require the construction of specialized alignment equipment, but also the required flux introduces contaminants. Cleaning steps must be added to the assembly operation to remove the flux and its remanents, and, even so, constraints are placed on the metallurgies and process flow when the necessity of flux is introduced. In addition, the possibility of misalignment, and thus lowered yield, is presented.
In U.S. Pat. No. 3,457,639, a method of alignment of microcircuit devices on a substrate is disclosed which uses a photoresist wall on a printed circuit board to align tabs on integrated circuit packages to metal strips on the substrate. In the process disclosed in the patent, the emphasis is on aligning the tabs with the strips, where the tabs are themselves visible, as is the conductive pattern on the substrate. This process of the patent does not address the problems inherent in aligning bumps hidden by a silicon chip when mounting on pads on a substrate.